1. Field of the Invention
The present invention relates in general to verification of a functional logic system including multiple logical components and, more specifically, to a method and system for creating a logical representation of the functional logic system or sub-systems from a physical representation of the functional logic system or sub-systems.
2. Description of the Prior Art
With the advent of very large scale integration (VLSI) logic design, a process was needed to verify that logic designs functioned according to specification. A common method was to take the logic design, typically using the hardware description language (HDL) used to describe the actual logic design, and write a testbench simulation environment to verify the logic design. A testbench provides a hierarchical, static connection environment to the design, then dynamically provides input stimulus to the design and monitors for appropriate output behavior from the design. When the design is being verified in this type of simulation structure it is typically referred to as the Design Under Test (DUT).